OpenROAD tutorial: Open-Source ASIC Design for Computer Architects

Ibex RISC-V core
OpenROAD implementation of a RISC-V Ibex core


The OpenROAD Project was founded in 2018 under the DARPA IDEA program to address the issue of hardware design requiring too much effort, cost, and time. Since then, the project has shown great success in providing free, open-source implementation for ASIC designs in technology nodes as small as 7nm. Notably, OpenROAD has enabled first-time chip designers, hobbyists, and students to fabricate chips through the Google/Efabless/Skywater 130nm free shuttle program. Over 100 designs have been silicon-tested on the first two shuttle runs and hundreds more have been taped out.

OpenROAD provides a tremendous opportunity for researchers to perform design space exploration, collaborate, and construct real chips in a free and open-source manner. This tutorial will aim to:


This tutorial will cover using OpenROAD for both cutting-edge nodes (e.g. ASAP 7nm) and older nodes (e.g. Skywater 130nm).

In this tutorial, we will present:

For a more detailed overview, please see the program.

What’s Not Covered

This tutorial is intended to introduce ASIC implementation to those already conceptually familiar with RTL design (undergraduate level or equivalent). We do not cover RTL design techniques or RTL validation.

Content: CC BY-SA Austin Rovinski 2022 (get source code). Creative Commons License

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